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Preliminary
SPC122A
SOUND CONTROLLER WITH 128KB FLASH MEMORY
GENERAL DESCRIPTION The SPC122A is a CPU based two-channel speech/melody synthesizer including CMOS 8-bit microprocessor with 69 instructions, 128K-bytes of Flash ROM for speech and melody data (Speech is compressed by a 4-bit ADPCM with approx. 36 sec speech duration @ 7KHz sampling rate) and 128-byte working SRAM. external memory is capable of being extended up to 256K. Its
It provides Multi-Duty-Cycle output that can be
implemented for remote-control purposes. It includes two Timer/Counters, 28 Software Selectable I/Os, 2 audio current D/A outputs (or one PWM audio output) and serial interface I/O port. Volume control is also provided. For audio processing, melody and speech can be mixed into one output. It operates over a wide
voltage range of 2.4V - 5.5V. In addition, the SPC122A has a Clock Stop mode for power savings. The power savings mode saves the RAM contents, but freezes the oscillator, causing all other chip functions to be inoperative. The Max. CPU clock frequency is 6.0MHz. (min.) - 6 clock cycles (max.). It has an Instruction Cycle Rate of 2 clock cycles
The SPC122A includes, not only the latest technology, but also the full
commitment and technical support of Sunplus.
FEATURES 8-bit microprocessor Provides 128K-byte Flash ROM for program and audio data 128-byte working SRAM Software-based audio processing
XI
Multi-Duty-Cycle outputs (1/2, 1/3, 1/4 duty)
BLOCK DIAGRAM
8-Bit RISC controller 128K-byte flash ROM 128-byte SRAM Timer TimeBase INT Control
Wide operating voltage: 2.4V - 3.4V @ 2.0MHz 3.6V - 5.5V @ 6.0MHz Supports Crystal Resonator or Rosc (with bonding option) Max. CPU clock: 2.0MHz @ 3V, 6.0MHz @ 5V Standby mode (Clock Stop mode) for power savings. Max. 2 A @ 5V 500ns instruction cycle time @ 4.0MHz CPU clock Provides 28 general I/Os Two 12-bit timer/counters 6 INT sources Key wake-up function Approx. 36 sec speech @ 7KHz sampling rate with ADPCM Two 8-bit D/A output One PWM audio output (single speaker) Volume control function Sunplus Technology Co., Ltd. 1
Rosc XO
A17 A16-0 ROMOE D7-0 BURN SPOP CE
flash program controller
Serial interface I/O
Two 8-bit D/A (current) or PWM output
AUD1
AUD2
28
PINS
GENERAL
I/O
PORT
IOA3-0 (I/O)
IOB7-0 (I/O)
IOC7-0 (I/O)
IOD7-0 (I/O)
APPLICATION FIELD Intelligent education toys Ex. Pattern to voice (animal, car, color, etc.) Spelling (English or Chinese) Math High end toy controller Talking instrument controller General speech synthesizer Industrial controller Rev.: 0.3 1999.11.18
Preliminary
SPC122A
FUNCTION DESCRIPTIONS CPU The SPC122A 8-bit microprocessor is a high performance processor equipped with Accumulator, Program Counter, X Register, Stack pointer and Processor Status Register (this is the same as the 6502 instruction structure). SPC122A is able to perform with 6.0MHz (max.) depending on the application specifications.
OSCILLATOR The SPC122A supports AT-cut parallel resonant oscillated Crystal / Resonator or RC Oscillator or external clock sources by using the bonding option (select one from those three types). The design of application circuit should follow the vendors' specifications or recommendations. X'TAL/ROSC circuits for most applications: The diagrams listed below are typical
SPC122A
XI/R XO
VDD Rosc 20 pf 20 pf
SPC122A
XI/R XO
(a) Crystal or Ceramic Resonator Connections
(b) RC Oscillator Connections
BONDING OPTION The SPC122A has the following bonding option: Supports Crystal Resonator or Rosc (with bonding option).
ROM AREA The SPC122A provides a 122AK-byte of Flash ROM that can be defined as the program area, audio data area, or both. To access ROM, users should program the BANK SELECT Register, choose bank, and access address to fetch data. The combination of CE and Burn pins is capable of programming the Flash ROM as In addition,
parallel mode. In contrast, using CE and STOP pins can program the Flash ROM as serial mode. pin AD17 and CE can be used to extend the memory from 128K to 256K with external memory.
RAM AREA The SPC122A total RAM consists of 128 bytes (including Stack) at locations from $80 through $FF.
Sunplus Technology Co., Ltd.
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Rev.: 0.3
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Preliminary
SPC122A
MAP OF MEMORY AND I/Os
*I/O PORT: - PORT IOA $0002 IOB IOC IOD $0003 $0004 $0005 $00100 USER RAM and STACK $00200 UNUSED - INTA (from TIMER A) $00600 *INT SOURCE: - INTA (from TIMER A) - INTB (from TIMER B) - CPU CLK / 1024 - CPU CLK / 8192 - CPU CLK / 65536 - EXT INT - Capable of being extended to 256K with external memory $1FFFF $08000 USER'S PROGRAM & DATA AREA ROM BANK #0 SUNPLUS TEST PROGRAM *MEMORY MAP (From ROM view) $00000 HW register, I/Os
- I/O CONFIG $0000 $0001 *NMI SOURCE:
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Rev.: 0.3
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Preliminary
SPC122A
I/O PORT CONFIGURATION*
Input/Output IOA port : IOA3 - 0 logic_1 control output data V DD 90K output data buffer or OD-NMOS logic_2 control OD : Open Drain OD-NMOS or buffer Input/Output IOB port : IOB2 - 0 input data
60K
input data OD : Open Drain
Input/Output IOB port : IOB5 - 4 input data OD-NMOS or buffer
Input/Output IOC port : IOC3 - 0 logic_4 control output data V DD 90K
output data logic_3 control OD : Open Drain
60K input data OD : Open Drain
buffer or OD-NMOS
Input/Output IOD port : IOD3 - 0 input data OD-PMOS or buffer
Input/Output IOD port : IOD7 - 4 input data OD-PMOS or buffer
output data logic_5 control OD : Open Drain
output data 60K logic_6 control OD : Open Drain
60K
*Values shown are for VDD = 5.0V test conditions only.
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Preliminary
SPC122A
POWER SAVINGS MODE The SPC122A provides a power savings mode (Standby mode) for those applications that require very low stand-by current. To enter standby mode, the Wake-Up Register should be enabled and then stop the CPU In such a mode,
clock by writing the STOP CLOCK Register. The CPU will then go to the stand-by mode. RAM and I/Os will remain in their previous states until being awakened. source in the SPC122A.
Port IOD7-0 is the only wake-up
After the SPC122A is awakened, the internal CPU will go to the RESET State (Tw Wakeup Reset will not affect RAM or I/Os (See
65536 x T1) and then continue processing the program. FIG.1).
Sleep T1 CPU CLK Reset
Wake-up
Tw
FIG. 1 T1 = 1 / ( FCPU ), Tw 65536 x T1
MULTI-DUTY CYCLE MODE The SPC122A provides three output waveforms, 1/2, 1/3, and 1/4 duty cycles. The Control Register should be used to select 1/2, 1/3, or 1/4 duty cycle and the IOA2 should be programmed as the multi-duty cycle output port. Users can use the combinations of these duty cycles for remote-control purpose.
1/2, 1/3, 1/4 DUTY CYCLE OUTPUTS
Clock
1/2 duty cycle
1/3 duty cycle 1/4 duty cycle
SERIAL INTERFACE I/O The SPC122A provides serial interface I/O mode for those applications required large ROM/RAM. Serial
Interface I/O Port can be used to read/write data from/to extra memory. The interface I/O Register is the control register for programming interface I/O. Sunplus Technology Co., Ltd. 5 Rev.: 0.3 1999.11.18
Preliminary
SPC122A
TIMER/COUNTER The SPC122A contains two 12-bit timer/counters, TMA and TMB respectively. TMA can be specified as a
timer or a counter, but TMB can only be used as a timer. In the timer mode, TMA and TMB are re-loaded upcounters. When timer overflows from $0FFF to $0000, the carry signal will make the timer automatically reload to the user's pre-set value and be up-counted again. At the same time, the carry signal will generate the INT signal if the corresponding bit is enabled in the INT ENABLE Register. If TMA is specified as a counter, users can reset by loading #0 into the counter. After the counter has been activated, the value of the counter can
also be read from the counters at the same time.
Timer/Counter Clock source can be selected as follows: Timer/Counter TMA 12-BIT TIMER 12-BIT COUNTER TMB 12-BIT TIMER Clock Source CPU CLOCK (T) or T/4 T/64, T/8192, T/65536 or EXT CLK T or T/4 TMA only, select timer or counter Select T or T/4
MODE SELECT REGISTER TIMER CLOCK SELECTOR
SPEECH AND MELODY Since the SPC122A provides a large ROM and wide range of CPU operation speeds, it is most suitable for speech and melody synthesis.
For speech synthesis, the SPC122A can provide NMI for accurate sampling frequency.
Users can record or
synthesize the sound and digitize it into the ROM. The sound data can be played back in the sequence of the control functions as designed by the user's program. Several algorithms are recommended for high fidelity and compression of sound including PCM, LOG PCM, and ADPCM.
For melody synthesis, the SPC122A provides the dual tone mode. After selecting the dual tone mode, users only need to fill either TMA or TMB, or both TMA and TMB to generate expected frequency for each channel. The hardware will toggle the tone wave automatically without entering into an interrupt service routine. Users
are able to simulate musical instruments or sound effects by simply controlling the envelope of tone output.
VOLUME CONTROL FUNCTION The SPC122A contains a volume control function that provides an 8-step volume controller to control current D/A or PWM output. provided. A volume control function selector (Enable/Disable) register and controller register is
Sunplus Technology Co., Ltd.
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Rev.: 0.3
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Preliminary
SPC122A
Differences between SPC121A and SPC122A SPC121A 1. 2. 3. 4. 5. 6. 7. 8. Work range ROM type ROM SIZE I/O port SIO PWM Output Multiphase Output Volume Control 2.4V - 5.5V Mask 120K 21 SPC122A 3.6V - 5.5V Flash 128K 28
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Preliminary
SPC122A
PIN DESCRIPTIONS* Mnemonic VDD PIN No. 5 29 34 45 57 VSS 17 27 50 66 XI 32 I Oscillator crystal input or RESISTOR (Resistor should be connected to VDD) XO OPT* BURN 31 30 15 16 14 18 4 19 36 33 35 6-13 74-60 3-1 Port A is an 8-bit bi-directional programmable Input / Output port with IOA0 IOA1 IOA2 IOA3 46 47 48 49 I/O I/O I/O I/O Pull-high or Open-drain option. Pure or Pull-high states. As inputs, Port A can be in either the O I I I I/O I O I I O O I/O I/O Data Bus Address Bus Oscillator crystal output For ROSC option, OPT should be connected to VDD. Burn, This pin is an active high to select the flash ROM program function This pin is an active low to select this chip as a 1Mbits memory Data Output enable Serial program option Extended Memory Enable This pin is an active low reset to the chip. TEST MODE AUDIO OUTPUT I Ground reference for logic and I/O pins Type I Description Positive supply for logic and I/O pins
CE ROMOE
SPOP A17 RESET TEST AUD1 AUD2 D7 - 0 A13 - 0 A16 - 14
As outputs, Port A can be either Buffer or
Open-drain NMOS types (Sink current). IOA0: Serial programming clock output IOA2: Multi-duty cycle output **See note 1 and 2 below.
Sunplus Technology Co., Ltd.
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Preliminary
SPC122A
Mnemonic PIN No. Type Description Port B is an 8-bit bi-directional Input / Output port with Pull-low or OpenIOB0 IOB1 IOB2 IOB4 IOB5 IOB6 IOB7 59 58 56 54 53 52 51 I/O I/O I/O I/O I/O I/O I/O **See note 1 and 2 below. Port C is an 8-bit bi-directional Input / Output port with Pull-high or OpenIOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 28 26 25 24 23 22 21 20 I/O I/O I/O I/O I/O I/O I/O I/O **See note 1 and 2 below. Port D is an 8-bit bi-directional Input / Output port with Pull-low or OpenIOD0 IOD1 IOD2 IOD3 IOD4 IOD5 IOD6 IOD7 44 43 42 41 40 39 38 37 I/O I/O I/O I/O I/O I/O I/O I/O **See note 1 and 2 below. drain option. As inputs, Port D can be either Pure or Pull-low states. drain option. As inputs, Port C can be in either the Pure or Pull-high drain option. As inputs, Port B can be in either the Pure or Pull-low
states. As outputs, Port B can be either Buffer or Open-drain NMOS types (Sink current).
states. As outputs Port C can be a Buffer or Open-drain NMOS type (sink current). IOC0: Serial programming Data IOC1: EXT INT PIN IOC2: EXT COUNT IN
As outputs, Port D can be either Buffer or Open-drain PMOS (send current). (Port D can be software programmed for wake up I/O)
* Refer to SPC Programming Guide for complete information. **Note: 1.) Two input states can be specified; Pure Input, Pull-High or Pull Low. 2.) Three output states can be specified as Buffer output, Open Drain PMOS output (send), or Open Drain NMOS output (sink). ***OPT is the selection pin for ROSC or X'TAL using the bonding option. The shape looks like the figure at the right. VDD. When ROSC is selected, OPT is connected to
VDD OPT
If X'TAL is selected, OPT is floating. The reason OPT is near VDD is that
when ROSC is selected, it is easy to make the connection between VDD and OPT.
Sunplus Technology Co., Ltd.
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Rev.: 0.3
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Preliminary
SPC122A
ABSOLUTE MAXIMUM RATINGS Characteristics DC Supply Voltage Input Voltage Range Operating Temperature Storage Temperature Symbol V+ VIN TA TSTO Ratings < 7V -0.5V to V+ + 0.5V 0 -50 to +60 to +150
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational conditions see AC/DC Electrical Characteristics.
AC CHARACTERISTICS ( TA = 25 Characteristics Symbol
) Limit Unit Min. Typ. 1.0 4.0 Max. 2.0 6.0 6.0 MHz MHz MHz VDD = 3V VDD = 5V FCPU = FOSC2 @5V Test Condition
OSC Frequency CPU Clock
FCPU FCPU -
DC CHARACTERISTICS ( TA = 25 Characteristics Operating Voltage Operating Current Standby Current Audio output current Input high level Input Low level Output high I IOA, IOB, IOD Output sink I IOA, IOB, IOD Input resistor IOA, IOB, IOC, IOD Symbol
, VDD = 5V ) Limit Unit Min. Typ. 6.5 -3.0 Max. 5.5 8.0 2.0 0.8 V mA A mA V V mA For 3-battery FCPU = 4.0MHz@5V, no load VDD = 5V VDD = 5V VDD = 5V VDD = 5V VDD = 5V VOH = 4.2V VDD = 5V VOL = 0.8V Pull Low VDD = 5V 3.6 3.0 -1.0 Test Condition
VDD IOP ISTBY IAUD VIH VIL IOH
IOL
4.0
-
-
mA
RIN
-
60
-
kohm
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Preliminary
SPC122A
The relationship between the Rosc and the Fosc VDD = 3.0V , Ta = 25 VDD = 4.5V , Ta = 25
6.0 5.0 4.0 3.0 2.0 1.0 0.0 0 200 400 Rosc ( Kohms ) 600 800
4.0 3.0 2.0 1.0 0.0 0 200 400 600 800 Rosc ( Kohms )
FCPU ( MHz )
Frequency vs. Temperature
Frequency normalized to 25 1.04
A
Frequency vs. VDD
FCPU ( MHz )
Rosc=100Kohms VDD=4.5V
4.0 FCPU ( MHz ) 3.0
Rosc = 91 Kohms
FCPU/FCPU(25
A1.02
1.00 0.98 0.96 0 10
)
2.0 1.0 0.0 2.0 3.0 4.0 5.0 VDD ( Volts )
Rosc = 470 Kohms
VDD=3.0V
20 30 40 50 60 Temperature ( )
A
70
Operating current vs. Frequency vs. VDD
5.0 4.0 IOP ( mA ) 3.0 2.0 1.0 0.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 FCPU ( MHz )
VDD = 3V VDD = 4.5V
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Rev.: 0.3
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SPC122A
X'TAL/CERAMIC OSC C3 20p C4
VDD
VDD
VDD
Speaker 20p Q1 8050D IOA3 ~ 0 IOC7 ~ 0
VDD
XI OPT
R1 Resistor
Speaker
IOA3 ~ 0
XI OPT IOA (I/O)
XO
A17 A16-A0 ROMOE D7-0
Preliminary
C1 + 0.47 F
XO A17 A16-A0 ROMOE D7-0
IOA (I/O)
C1 + 0.47 F
Q1 8050D
IOC7 ~ 0
IOC (I/O)
AUD1 VDD
IOC (I/O)
AUD1
SPC122A
IOB7 ~ 0
IOB(I/O) VDD AUD2
SPC122A
IOB7 ~ 0
IOB(I/O) VDD AUD2 220A F 0.1A
VDD
IOD7 ~ 0
IOD (I/O) RESET
C6 0.1 Speaker
IOD7 ~ 0
IOD (I/O) VSS RESET
C4 0.1 Speaker
220A F 0.1A
C5
APPLICATION CIRCUIT NOTES
RESET
Application Circuit Note (1)
SPC122A Application circuit (D/A Output)
Sunplus Technology Co., Ltd.
0.1
C2 + 0.47 F
Q2 8050D C3 RESET 0.1
C2 + 0.47 F
Q2 8050D
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SPC122A
VDD
VDD
VDD
C3 20p
VDD XI OPT IOA0 IOA1 IOA2 IOA3 IOC0 XO A17 A16-A0 ROMOE D7-0 AUD1
C4 Speaker 20p
VDD
R1 Resistor Q1 8050D
SPRS 256A
XI XO A17 A16-A0 ROMOE D7-0 AUD1
Speaker
Preliminary
SPRS 256A
VDD SCL CS SDA VSS
C1 + 0.47 F
VDD SCL CS SDA VSS
OPT IOA0 IOA1 IOA2 IOA3 IOC0
Q1 8050D C1 + 0.47 F
IOC7~1 IOB7~0
SPC122A
IOC(I/O) VDD IOB(I/O) AUD2 220A F 0.1A
IOC7~1
VDD
SPC122A
IOC(I/O) VDD IOB(I/O) AUD2
IOB7~0 C6 0.1 Speaker IOD7~0
IOD (I/O) RESET
IOD7~0
IOD (I/O) RESET VSS
VSS
C4 0.1 Speaker
220A F 0.1A
Application Circuit Note (2)
C5 RESET 0.1
C3 RESET 0.1
SPC122A Application circuit with Serial Interface I/O Application
Sunplus Technology Co., Ltd.
Q2 8050D C2 + 0.47 F
Q2 8050D C2 + 0.47 F
13
VDD
Rev.: 0.3
X'TAL/CERAMIC OSC
1999.11.18
SPC122A
X'TAL/CERAMIC OSC C3 20p
XO A17 A16-A0 ROMOE D7-0 AUD1 IOC (I/O)
VDD
C4 20p
VDD
XI XI XO A17 A16-A0 ROMOE D7-0 AUD1
R1 Resistor
IOA3 ~ 0
OPT IOA (I/O)
IOA3 ~ 0 IOC7 ~ 0
OPT IOA (I/O)
Preliminary
IOC7 ~ 0
IOC (I/O)
SPC122A
IOB7 ~ 0
IOB(I/O) AUD2 VDD
Speaker ~16A
VDD
SPC122A
IOB7 ~ 0
IOB(I/O) AUD2 VDD IOD (I/O) VSS RESET 0.1
IOD7 ~ 0
IOD (I/O) VSS RESET 0.1 220A F
IOD7 ~ 0
A
220A F
Application Circuit Note (3)
C5 RESET 0.1
C3 0.1
Sunplus Technology Co., Ltd.
RESET
SPC122A Application circuit (PWM Output)
A
14
VDD
A
Speaker ~16
Rev.: 0.3
1999.11.18
SPC122A
X'TAL/CERAMIC OSC C3 20p
VDD
VDD SCL CS SDA VSS
VDD
C4 20p
VDD XI OPT IOA0 IOA1 IOA2 IOA3 IOC0 XO A17 A16-A0
ROMOE
VDD SCL CS SDA VSS
R1 Resistor
XI OPT IOA0 IOA1 IOA2 IOA3 IOC0 XO A17 A16-A0 ROMOE D7-0 AUD1
Preliminary
SPRS 256A
D7-0 AUD1
SPRS 256A Speaker ~16A
VDD
IOC7~1 IOB7~0 IOD7~0
SPC122A
IOC(I/O) AUD2 VDD 0.1A IOD (I/O) RESET VSS IOB(I/O)
IOC7~1 IOB7~0 IOD7~0
SPC122A
IOC(I/O) AUD2 IOB(I/O) VDD 0.1A IOD (I/O) RESET VSS VDD
Speaker ~16A
220 F
A
220A F
C5
Application Circuit Note (4)
C3 0.1
Sunplus Technology Co., Ltd.
RESET 0.1
RESET
SPC122A Application circuit with Serial Interface I/O Application
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Rev.: 0.3
1999.11.18
SPC122A
X'TAL/CERAMIC OSC C3 20p
XI XO D7-0 A16-A0 IOA(I/O) ROMOE A17 AUD1 IOC(I/O)
VDD
C4 20p
VDD
VDD D7~0 A16~0 OE CE VSS
R1 Resistor
VDD 128K Memory XI XO D7-0 A16-A0 ROMOE A17
VDD
VDD D7~0 A16~0 OE CE VSS
IOA3~0
OPT
IOA3~0
OPT IOA(I/O)
128K Memory
Preliminary
IOC7~0
IOC7~0
Speaker ~16A
VDD IOC(I/O)
AUD1
AUD2 IOB(I/O) VDD
AUD2 IOB(I/O) VDD VDD
IOD7~0
IOD (I/O) 0.1
IOD7~0
A
220A F IOD (I/O) RESET VSS 0.1A 220A F
RESET VSS
Application Circuit Note (5)
C5 RESET 0.1
C3 0.1
Sunplus Technology Co., Ltd.
RESET
SPC122A Application circuit with extension memory from 128K to 256K
16
IOB7~0
SPC122A
SPC122A
IOB7~0
Speaker ~16A
Rev.: 0.3
1999.11.18
SPC122A
VDD VDD
VDD
VDD SUNPLUS WRITER
Preliminary
A16-0 D7-0 ROMOE
IOA0
IOC0
SUNPLUS WRITER
SPC122A
VDD BURN CE IOB0 IOB1 IOB2 VSS PGMB VDD
SPC122A
SPOP CE
GND
VSS VSS VSS
VSS
Application Circuit Note (6)
PARALLEL PROGRAMMING METHOD
SERIAL PROGRAMMING METHOD
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Preliminary
SPC122A
PAD ASSIGNMENT AND LOCATIONS PAD Assignment
Chip Size: 3250 m x 3500 m This IC substrate should be connected to VSS
Note: To ensure that the IC function properly, bond all VDD, VSS, AVDD and AVSS pins.
Ordering Information Product Number SPC122A-nnnnV-C Note1: Code number (nnnnV) is assigned for customer. Note2: Code number (nnnn = 0000 - 9999); version (A = A - Z). Package Type Chip form
NOTE: SUNPLUS TECHNOLOGY CO., LTD reserves the right to make changes at any time without notice in order to improve the design and performance and to supply the best possible product.
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Preliminary
SPC122A
PAD Locations Pad No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 61 62 63 64 Pad Name A14 A15 A16 A17 VDD D7 D6 D5 D4 D3 D2 D1 D0 X -1429 -1429 -1429 -1429 -1424 -1429 -1429 -1429 -1429 -1429 -1429 -1429 -1429 -1429 -1417 -1417 -1417 -1397 -1401 -1422 -1433 -1424 -1134 -994 -851 -699 -573 -416 -259 -81 675 535 394 254 Y 1538 1388 1247 1107 956 806 666 525 385 245 104 -36 -176 -316 -466 -641 -791 -979 -1126 -1285 -1412 -1570 -1568 -1557 -1558 -1559 -1547 -1562 -1549 -1541 1547 1547 1547 1547 19 Pad No 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 68 69 70 71 Pad Name XO XI AUD1 VDD AUD2 TEST IOD7 IOD6 IOD5 IOD4 IOD3 IOD2 IOD1 IOD0 VDD IOA0 IOA1 IOA2 IOA3 VSS IOB7 IOB6 IOB5 IOB4 IOB3 IOB2 VDD IOB1 IOB0 A0 A7 A8 A9 A10 X 81 247 508 847 1186 1441 1426 1432 1432 1434 1426 1427 1427 1424 1416 1433 1433 1426 1428 1400 1432 1437 1432 1443 1440 1426 1421 1113 972 816 -309 -458 -598 -739 Rev.: 0.3 Y -1542 -1542 -1574 -1574 -1574 -1542 -1320 -1182 -1038 -906 -759 -620 -485 -342 -197 -43 98 238 381 564 754 895 1040 1164 1303 1441 1582 1547 1547 1547 1547 1547 1547 1547 1999.11.18
ROMOE
BURN
CE
VSS SPOP RESET IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 VSS IOC0 VDD OPT A1 A2 A3 A4
Sunplus Technology Co., Ltd.
Preliminary
SPC122A
Pad No 65 66 67 Pad Name A5 VSS A6 X 113 -29 -169 Y 1547 1537 1547 Pad No 72 73 74 Pad Name A11 A12 A13 X -879 -1020 -1160 Y 1547 1547 1547
DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by
description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. prices at any time without notice. SUNPLUS reserves the right to halt production or alter the specifications and Accordingly, the reader is cautioned to verify that the data sheets and other Products described herein are intended for
information in this publication are current before placing orders. use in normal commercial applications.
Applications involving unusual environmental or reliability
requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. illustrated in this document are for reference purposes only. Please note that application circuits
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Rev.: 0.3
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